1. Field of the Invention
The present invention relates to a dynamic random access memory (DRAM) structure, and particularly to a DRAM structure having a merged trench and stack capacitor.
2. Description of the Prior Art
Along with the development of miniaturization of various electronic products, the design of the dynamic random access memory (DRAM) elements has to match the requirement of high integration and high density. DRAMs with trench capacitors have become one of the main structures of high-integrated DRAM products. Such DRAMs contain trench capacitors fabricated inside deep trenches that are formed in a semiconductor substrate by an etching process so as to well utilize space of chips to effectively reduce memory cell size. However, trench-type DRAMs, as well as stack-type DRAMs, have encountered the feature size limitation, and it is difficult to increase capacitance of the capacitor of the memory cell laid out within the limited size.
U.S. Pat. No. 5,920,785 discloses a twin bit DRAM cell capable of storing two bits of digital data as stored charge within the DRAM cell, which has two pass transistors, a trench capacitor structure, and a stack capacitor structure. The pass transistors each have a source connected to a bit line voltage generator to control placement of the charge within the twin bit DRAM cell, a gate connected to a word line voltage generator to control activation of the DRAM cells, and a drain. In such way, the trench capacitor structure and the stack capacitor structure are each an individual capacitor and independently employed, and, accordingly, the maximal capacitance exhibited is only the capacity of the respective capacitors.
U.S. Pat. No. 6,018,177 discloses a DRAM cell capable of storing two bits of digital data as four levels of stored charge within the DRAM cell. The four level DRAM cell has a pass transistor, a trench capacitor structure, and a stack capacitor structure. The pass transistors has a source connected to a bit line voltage generator to control placement of the charge within the four level DRAM cell, a gate connected to a word line voltage generator to control activation of the DRAM cells, and a drain. The trench capacitor structure has a top plate connected to the drain and a bottom plate connected to a substrate biasing voltage source. The stack capacitor structure has a first plate connected to the drain and a second plate connected to a coupling-gate voltage generator. The coupling-gate voltage generator will provide four levels of voltage that will indicate the level of charge to be stored within the four level DRAM cell. An interconnecting block will interconnect the top plate of the trench capacitor structure to the first plate of the stack capacitor structure. The interconnection point between the trench capacitor structure and the stack capacitor structure will form the storage node that will retain the level of charge to indicate the state of the two bits of digital data. In such way, the trench capacitor structure has an electrode connecting to the substrate biasing voltage source, and the stack capacitor structure has an electrode connecting to the coupling-gate voltage generator. Accordingly, the two capacitors are each an individual capacitor and independently employed, and the maximal capacitance obtained is only the capacity of the respective capacitors, not the sum.
Therefore, there is still a need for a novel DRAM structure having an increased capacitance within the feature size limitation to match the demand of high integration and high density.